Why Code Storage Survived: The Niche Logic Behind NOR Flash
Trends · Published 2026-08-28 · Updated 2026-08-28
3D NAND crushed cost per bit, yet NOR never got squeezed out — because code storage rewards reliability, random execution and long supply, not density.
3D NAND drove cost per bit to a place NOR cannot follow, yet code storage never left the board. The reason is not process technology but the job the part holds. The first instruction after power-up has to come out of this chip, so it needs random reads, execute-in-place and a part number that stays buyable for a decade. Capacities stop at a few MB to a few hundred Mb, so shrinking saves little wafer area while a mature line still pays for itself. The decisive factor is risk: one cheap component carries the entire consequence of a system that will not boot, so customers swap far less readily than the price gap suggests. The pool is small and price-inelastic, which is why a newcomer breaks even only by selling flash alongside an MCU.
The job sets the spec
Fetch on power-up: the boot medium has to hand over a correct instruction within milliseconds of a stable rail, with no retry. Random read and execute-in-place: code is fetched at arbitrary addresses rather than copying a page into a buffer, correcting it and mapping out bad blocks first. Bit-level reliability, plus ten years of the same part number.
A claim worth arguing with: the line between NOR and NAND is not capacity but access model. NAND is read by page and block and leans on bad-block management and ECC mapping, so it cannot fetch an instruction — structurally, not because its density is too low. That is why the capacity race is beside the point here. NAND improves in cost per bit; NOR improves in certainty between power-on and the first instruction. The first can be stacked into existence, the second only verified.
Shrinking never earned this capacity band
Stacking pays where capacity is the product. On the same generation of NAND line, a 1Tb QLC wafer is quoted at $25.00 and a 1Tb TLC wafer at $29.00 — bits per area converted straight into money. A few MB to a few hundred Mb of NOR behaves differently: the die is already small, doubling density saves limited area, and the bill arrives as another full reliability requalification.
So NOR rests on depreciation and stable yield rather than leading-edge technology. It survives price wars because it needs no new equipment to defend cost, and it cannot grow into a high-capacity business. The directory records say this plainly. Macronix runs MX25 NOR Flash as its main code-storage line beside industrial SLC NAND and masked ROM; Winbond positions W25Q NOR Flash as the global code-storage leader while also shipping SLC NAND, HyperRAM and W77Q secure flash. Both are annotated as global NOR leaders, one adding niche DRAM supply, the other automotive and industrial storage — effort spent on neighbouring positions instead of chasing NAND.
| Dimension | Code storage (NOR) | Data storage (NAND) |
|---|---|---|
| Read model | Fetch at any address, run in place | Page and block reads, then ECC and mapping |
| Cost driver | Depreciated lines and yield | Stack layers and cost per bit |
| Willingness to swap | Very low, it owns boot failure | Moderate, dies can be re-blended |
Switching cost outruns the price gap
The failure mode of a boot flash is a bricked unit, and the warranty lands on the design house, not the memory vendor. Requalifying means power-on sequencing and voltage window, the controller's QSPI/XSPI compatibility list, temperature grade, firmware update and rollback, plus programming fixtures and serial-number flows. Spread over a programme, that labour usually costs more than a year of the saving. Buyers stay put for arithmetic, not inertia.
The barrier is therefore years inside customer platforms, not IP strength. A challenger's route is not single-part price comparison but riding an ecosystem: GigaDevice's SPI NOR Flash is positioned as the domestic code-storage workhorse, and it works best quoted with the GD32 line behind its leading domestic MCU shipment — an GD32F4 is pin-compatible with an STM32F4, so customers switch a whole design rather than a part number.
The honest downside
Two pressures are real. MCU on-chip flash is consuming external code storage: firmware fits inside, boot completes inside, and many small systems need no external NOR. And the border is taken by adjacent parts — HyperRAM picks up fetch-plus-extension-memory work, while eMMC and UFS controllers pull image and data into one location.
Growth for external NOR therefore sits in scenarios that require a separate boot medium: secure boot with firmware rollback, multi-image SoC boards, modules reprogrammed in the field, firmware storage inside automotive modules such as Macronix's AEC-Q100 qualified automotive NOR. Reading this as a permanently useful but margin-limited position is closer to the truth than reading it as a market that will get bigger.
Notes for buyers
- Keep code storage and data storage as separate BOM blocks — boot flash, firmware image, parameters, logs; never let one NAND substitute for a boot NOR.
- Select in order: power-on timing and voltage, controller interface compatibility, temperature and reliability grade, long-term supply, then unit price.
- Treat W77Q-class secure flash as an architecture item — lock regions, rollback, line provisioning — not as a part swap.
- Separate automotive from industrial claims: AEC-Q100 is device-level, industrial rests on temperature range and endurance; both sit under the embedded storage category.
- Route frequently written logs and data to SLC NAND or a controller-based module instead of charging them onto NOR.
Data basis and limits
Only two lines from the ICNAV reference prices of 2026-10-26 are used here, the 1Tb QLC and 1Tb TLC wafer quotes (source CFM Flash Market, not live), and no trend conclusion is drawn from them. Company positioning and product-line names follow the curated directory records. Capacity ranges, qualification items and scenario splits are editorial judgement and can be disproved by project-level testing. Published and updated on 2026-08-28, with no revision for market moves; not procurement or investment advice.
Written by ICNAV 编辑部 · ICNAV editorial team. References: the ICNAV company directory and public industry sources.